Low-Capture-Power Test Generation for Scan-Based At-Speed Testing

Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0\u27s and 1\u27s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield lossIEEE International Conference on Test, 2005, 8 November 2005, Austin, TX, US

Efficient Test Set Modification for Capture Power Reduction

The occurrence of high switching activity when the response to a test vector is captured by flipflops in scan testing may cause excessive IR drop, resulting in significant test-induced yield loss. This paper addresses the problem with a novel method based on test set modification, featuring (1) a new constrained X-identification technique that turns a properly selected set of bits in a fullyspecified test set into X-bits without fault coverage loss, and (2) a new LCP (low capture power) X-filling technique that optimally assigns 0’s and 1’s to the X-bits for the purpose of reducing the switching activity of the resulting test set in capture mode. This method can be readily applied in any test generation flow for capture power reduction without any impact on area, timing, test set size, and fault coverage

An Improved Method of Per-Test X-Fault Diagnosis for Deep-Submicron LSI Circuits

Per-test diagnosis based on the X-fault model is an effective approach for a circuit with physical defects of nondeterministic logic behavior. However, the extensive use of vias and the unpredictable order relation among threshold voltages at fanout branches, both being typical phenomena in a deep-submicron circuit, have not been fully addressed by conventional per-test X-fault diagnosis. To solve these problems, this paper proposes an improved per-test X-fault diagnosis method, featuring (1) an extended X-fault model to handle vias and (2) occurrence probabilities of logic behavior for a physical defect to handle the unpredictable relation among threshold voltages. Experimental result show the effectiveness of the proposed method.7th Workshop on RTL and High Level Testing (WRTLT`06), November 23-24, 2006, Fukuoka, Japa

A method of reducing aliasing in a built-in self-test environment

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Improved test generation for high-activity circuits

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Built-in self-testing of random-access memories

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ALTERNATIVE TO SCAN DESIGN METHODS FOR SEQUENTIAL MACHINES

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